Communication technology has transformed our world. As the amount of information communicated over networks has increased, high speed transmission has become ever more critical. High speed communications often rely on the presence of high bandwidth capacity links between network nodes. For optical links, a transceiver module at one network node converts electrical data into optical data for transmission on the optical channel. At the other network node, another transceiver module receives the optical signal, and converts the signal into an electrical signal. Transceivers are equipped with transmit and receive channels, such that bi-directional communication is possible.
Presently, standards are being developed for optical links at a staggering speed of 100 Gigabits per second (sometimes abbreviated as “100 G”). In fact, the Institute for Electrical and Electronics Engineers, Inc. (often referred to as “IEEE” for short), a leading professional association in the art of networking technologies, has recently voted that the next generation of Ethernet technology will be 100 Gigabit Ethernet as well as some support for 40 Gigabit Ethernet, and has established several task forces to develop appropriate standards that are yet under development.
Currently, 100 G Single Mode Fiber (SMF) and Multi Mode Fiber (MMF) standards for Ethernet optical link applications are under development. In general, however, on the transmit side, it is presently contemplated that such high speed transmitters will include a Media Access Control (MAC) component that provides data electrically to an optical transmitter. However, since 100 Gigabits per second is simply too fast for present Complementary Metal Oxide Semiconductor (CMOS) electrical I/O technology, the 100 Gigabits of electrical data will be provided in several independent electrical lanes.
For instance, perhaps 10 lanes of 10 Gigabits per second of data will be provided from the MAC component to the transmitter. If there were additional overhead used for encoding or error correction, perhaps the data rate for each lane may be increased and/or the number of lanes may be increased. For instance, 66B/64B encoding has been contemplated as being used to encode each lane of 10 Gigabits of second. This would result in each of the 10 lanes of electrical traffic being at an actually data rate of 10.3125 Gigabits per second.
In the transmitter, the 10 lanes of electrical traffic are serialized down to perhaps 4 lanes of optical data, each at a data rate of 25.78125 Gigabits per second, which includes the overhead for 66B/64B encoding. These 4 lanes of optics may then be multiplexed onto a signal fiber using Wavelength Division Multiplexing (WDM).
Ethernet data may be transported over longer distances by Dense Wavelength Division Multiplexing (DWDM) systems. Currently, standards are under development for defining the use of DWDM technology for transporting 100 G Ethernet data. The standard is referred to as OTU4 and encapsulates the Ethernet data in a payload which is then Forward Error Correction (FEC) encoded. The resulting fiber data rate is approximately 112 Gigabits per second.
The system (hereinafter called the “100 G DWDM OTU4 system”) is contemplated as including two primary components, a Forward Error Correction capable MAC layer (called herein after an OTU4/FEC processor) and a 100 G DWDM capable transponder. In each of the transmit and receiver channels, there are 11 lanes of 11 Gigabits per second that are communicated using the OIF SFI-S interface specification. There is an eleventh de-skew lane to align all 10 data lanes for serial data transmission.
One of the modulation technologies considered in this 100 G DWDM OTU4 system is Dual-Polarization Quadrature Phase-Shift Keying (called “DP-QPSK” for short). The 112 Gigabit per second data stream is contemplated to be divided into four 28 Gb/s data streams, and modulates both I and Q phases of the TE and TM polarization states of the optical carrier wavelength.
FIG. 1 illustrates a possible architecture of a 100 G DWDM OTU4 system 100. On the transmit side, the system 100 receives 11 lanes (labeled collectively 111) of 11 Gigabits per second data. One lane 111A is received into an SFI-S decoder 112, and the remaining 10 lanes are received into a 10:4 serializer 113. The SFI-S decoder 112 and the serializer 113 receive reference clock signal REF_CLK in order to maintain proper timing. The data is reduced to four lanes (labeled collectively 115) of 28 Gigabit per second data after being properly encoded using pre-coder 114. A two-channel DP-QPSK modulator 116 applies DP-QPSK modulation to the four lanes of data to thereby modulate all four lanes of data onto a single optical fiber 117. The modulation is accomplished by using both the TE polarization and TM polarization of the optical signal as orthogonal information transport mechanisms, and also by using the in-phase and quadrature-phase portions of each polarization.
On the receive side, a receive optical signal (at a 112 Gigabit per second data rate) is received from the optical fiber 121 into a two-channel demodulator 122. The received optical signal may be formulated by another network node in the same manner as the optical signal that was transmitted by transmitter 116. The two-channel demodulator 122 extracts four components of the optical signal as follows: 1) an in-phase portion of the signal that had TE polarization (labeled TE-I), 2) a quadrature-phase portion of the signal that had TE polarization (labeled TE-Q), 3) an in-phase portion of the signal that had TM polarization (labeled TM-I), and 4) a quadrature-phase portion of the signal that had TM polarization (labeled TM-Q). Each of the TE and TM polarizations has a bit rate of 56 Gigabits per second, and a symbol rate of 28 Gigasymbols per second, the symbols each representing two bits of information.
The four demodulated data signals TE-I, TE-Q, TM-I and TM-Q are then quantized by a bank of four Analog-to-Digital Converters (ADCs) 123. Each ADC quantizes the correspond demodulated data signal into an n1 bit digital signal, which is then provided to a two-channel baseband Digital Signal Processor (DSP) 124. A local oscillator control signal “LO Control” is provided by the DSP 124 to the demodulator 122 thereby enabling a coherent receiver architecture. The DSP 124 identifies a corresponding point in an IQ symbol constellation chart for each of the TE and TM polarizations, and outputs the corresponding 2 bit sequence for each. The bit sequences are decoded by the decoder 125, after which the 4:10 deserializer 126 and SFI-S encoder 127 deserializes the bits into 11 lanes (referenced collectively as 128) of SFI-S encoded data, each at approximately 11 Gigabits per second.
Each ADC in the ADC bank 123 meets the Nyquist sampling criteria, which specifies that in order to properly sample an analog signal at a particular frequency, the sampling rate should be at least twice the particular frequency. Here, Fadc is twice Baud sampling, although slower Fadc may suffice at the expense of additional complexity in the DSP 124. The optimal ADC quantization bit precision level (n1) depends on the required PMD tracking performance, and can for example be 5 bits (i.e., n1=5).
FIG. 2 illustrates a conventional conceptualization 200 for the two-channel DP-QPSK transmitter 116 of FIG. 1. There are two polarization branches in FIG. 2, a TE polarization branch represented by the upper circuitry, and a TM polarization branch represented by the lower circuitry. Portions of a Distributed FeedBack (DFB) laser signal 201 are fed into each polarization branch via the use of a power splitter 202.
As for the TE branch, the continuous waveform from the DFB is fed into a hybrid IQ circuit 211, which essentially causes a continuous in-phase waveform to be provided to an in-phase modulator 212A, and a 90 degree phase shifted version of the continuous waveform (i.e., a quadrature-phase waveform) to be provided to the quadrature-phase modulator 212B. A distinct 28 Gigabit per second signal is fed into each of the in-phase modulator 212A and the quadrature-phase modulator 212B causing appropriate phase shift keying of the optical signal. The in-phase and quadrature-phase keyed optical signals are then summed using optical summer 213.
The TM branch includes hybrid IQ circuit 221, in-phase modulator 222A, quadrature-phase modulator 222B, and summer 223, which may essentially be the same as the respective components 211, 212A, 212B, and 213 of the TE branch. However, the TM branch receives its own distinct pair of 28 Gigabits per second signals for appropriate phase shift keying. In addition, a TE to TM rotator 224 is provided to represent the summed keyed optical signals using TM polarization. The TE polarized signal and the TM polarized signal are then summed using optical summer 203, after which the summed optical signal may then be transmitted onto an optical fiber.
FIG. 3 illustrates a resulting four symbol constellation IQ graph 300 that results from each of the TM polarization signal and the TE polarization signal. There are four symbol points shown in the IQ graph 300. When a particular signal is received for a certain polarization, the magnitude of the in-phase component and the quadrature phase component is calculated. Based on that information, the closest symbol point is selected from the IQ graph 300. The corresponding 2 bit symbol (herein m1 is equal to 2) is then output to the decoder 125. This is done for each of the TE and TM polarization signals.
FIG. 4 illustrates an example architecture 400 for the four-channel demodulator 122 of FIG. 1. The optical signal is received into the TE TM splitter 401, which provides the TE polarized portion of the optical signal to the I/Q hybrid mixer 411 to start the TE branch of demodulation. The TE TM splitter 401 also provides the TM polarized portion of the TE polarized optical signal to the TM to TE rotator 402, which rotates the polarization of that optical signal to TE polarization. That optical signal is provided to the I/Q hybrid mixer 421 to start the TM branch of modulation.
The TE and TM polarization optical signals are mixed in I/Q Hybrids 411 and 421 respectively with a continuous waveform signal provided by a DFB laser 402 via the power splitter 403 with the timing of the continuous waveform controlled by the LO Control signal. The resulting mixed signals are then provided to corresponding photo-receivers 412A, 412B, 422A and 422B. Each corresponding electrical signal is adjusted to a normalized level by respective Variable Gain Amplifiers (VGAs) 413A, 413B 423A and 423B, after which they are subjected to clock recovery 414A, 414B, 424A and 424B. The clock recovery elements 414A, 414B, 424A and 424B should be viewed as functional transformations only, since the clock recovery may be provided for all channels using a single clock recorder circuit. This results in signals TE-I, TE-Q, TM-I and TM-Q described in FIG. 1. The VGA and Clock Recovery performance is improved by using error signals derived in the two-channel Baseband DSP.
As previously mentioned, the conventional 100 G DWDM OTU4 system 100 of FIG. 1 uses DP-QPSK. In other words, as just explained, separate QPSK modulation is performed for both the TE polarization and TM polarization of the optical signal. The TE polarized and TM polarized signals are then optically summed for transport over the optical fiber.
Another term for QPSK modulation is 4PSK modulation, referring to the 4 point symbol constellation. The symbols are all the same amplitude and are spaced 90 degrees apart (see FIG. 3).
The next higher order modulation is 8PSK, and has an 8 point symbol constellation. The symbols are all the same amplitude (i.e., the points are equidistant from the origin of the IQ constellation plot) and are spaced 45 degrees apart. An example of 8PSK modulation system is Enhanced Data rates for GSM Evolution (EDGE) for sending high speed digital data over GSM wireless networks.